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CS5510/11/12/13 16-bit and 20-bit, 8-pin ADC
Features
Delta-sigma Analog-to-digital Converter
- Linearity Error: 0.0015% FS - Noise-free Resolution: Up to 17 Bits
General Description
The CS5510/11/12/13 are low-cost, easy-to-use, analog-to-digital converters (ADCs) which use chargebalance techniques to achieve 16-bit (CS5510/11) and 20-bit (CS5512/13) performance. The ADCs are available in a space-efficient, 8-pin SOIC package and are optimized for measuring signals in weigh scale, process control, and other industrial applications. To accommodate these applications, the ADCs include a fourth-order modulator and a digital filter. When configured with an external master clock of 32.768 kHz, the filter in the CS5510/12 provides better than 80 dB of simultaneous 50 and 60 Hz line rejection, and outputs conversion words at 53.5 Sps. The CS5511/13 include an on-chip oscillator which eliminates the need for an external clock source. Low-power, flexible supply configurations, compact pinout, and ease of use make these products ideal solutions for cost-conscience and space-constrained applications.
Differential Bipolar Analog Inputs VREF Input Range from 250 mV to 5 V 50/60 Hz Simultaneous Rejection (CS5510/12) 16 to 326 Sps Output Word Rate On-chip Oscillator (CS5511/13) Power Supply Configurations:
- V+ = 5 V, V- = 0 V - Multiple Dual-supply Arrangements
Low Power Consumption
- Normal Mode, 2.5 mW - Sleep Mode, 10 W
Low-cost, Compact, 8-pin Package Lead-free Device Package Options
ORDERING INFORMATION See page 23.
V+ AIN+ 1X AINVREF ~0.8X Differential 4th-order Delta-sigma Modulator CS Digital Filter Output Control Logic SDO
SCLK Oscillator (CS5511/13 only) VClock Gen.
(CS5510/12 only)
http://www.cirrus.com
Copyright (c) Cirrus Logic, Inc. 2005 (All Rights Reserved)
AUG `05 DS337F3
CS5510/11/12/13
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4 ANALOG CHARACTERISTICS ................................................................................................ 4 DIGITAL CHARACTERISTICS ................................................................................................. 5 DYNAMIC CHARACTERISTICS .............................................................................................. 6 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 6 SWITCHING CHARACTERISTICS - CS5510/12 ..................................................................... 7 SWITCHING CHARACTERISTICS - CS5511/13 ..................................................................... 8 2. GENERAL DESCRIPTION ..................................................................................................... 10 2.1 Analog Input ..................................................................................................................... 10 2.1.1 Analog Input Model ............................................................................................. 10 2.2 Voltage Reference Input .................................................................................................. 10 2.2.1 Voltage Reference Input Model ........................................................................... 11 2.3 Power Supply Arrangements ........................................................................................... 11 2.3.1 Digital Logic Levels ............................................................................................. 11 2.4 Clock Generator ............................................................................................................... 14 2.4.1 External Clock Source for CS5510/12 ................................................................ 14 2.4.2 Internal Oscillator for CS5511/13 ........................................................................ 14 2.5 Performing Conversions .................................................................................................. 15 2.5.1 Reading Conversions - CS5510/12 ..................................................................... 16 2.5.2 Reading Conversions - CS5511/13 ..................................................................... 16 2.5.3 Output Coding ..................................................................................................... 17 2.5.4 Digital Filter ......................................................................................................... 18 2.5.5 Multiplexed Applications ...................................................................................... 19 2.6 Digital Off-chip System Calibration .................................................................................. 20 2.7 Power Consumption, Sleep and Reset ............................................................................ 20 2.8 PCB Layout ...................................................................................................................... 20 3. PIN DESCRIPTIONS .............................................................................................................. 21 4. SPECIFICATION DEFINITIONS ............................................................................................. 22 5. ORDERING INFORMATION ................................................................................................... 23 6. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION ............................ 23 7. REVISION HISTORY ............................................................................................................. 23 8. PACKAGE DIMENSIONS ....................................................................................................... 24
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
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LIST OF FIGURES
Figure 1. SDO Read Timing CS5510/12 (Not to Scale).................................................................. 9 Figure 2. SDO Read Timing CS5511/13 (Not to Scale).................................................................. 9 Figure 3. Input models for AIN+ and AIN- pins. ............................................................................ 10 Figure 4. CS5512/13 Measured Noise-Free Bits vs. VREF. ......................................................... 11 Figure 5. Input model for VREF pin............................................................................................... 11 Figure 6. CS5510/11/12/13 Configured with a +5.0 V Analog Supply. ......................................... 12 Figure 7. CS5510/11/12/13 Configured with 2.5 V Analog Supplies........................................... 12 Figure 8. CS5510/11/12/13 Configured with V+ = +3.3 V and V- = -1.7 V; or V+ = +3.0 V and V- = -2.0 V. .................................................................................... 13 Figure 9. CS and SCLK Digital Input Levels. ................................................................................ 14 Figure 10. SDO Digital Output Levels. .......................................................................................... 14 Figure 11. Serial Port Output Drive Logic. .................................................................................... 14 Figure 12. External (CMOS Compatible) Clock Source. ............................................................... 15 Figure 13. Using a Microcontroller as a Clock Source. ................................................................. 15 Figure 14. Typical Linearity Error for CS5510............................................................................... 15 Figure 15. Typical Linearity Error for CS5512............................................................................... 15 Figure 16. Data Word Timing for the CS5510............................................................................... 16 Figure 17. Data Word Timing for the CS5511............................................................................... 17 Figure 18. Data Word Timing for the CS5512............................................................................... 17 Figure 19. Data Word Timing for the CS5513............................................................................... 17 Figure 20. Digital Filter Response................................................................................................. 19
LIST OF TABLES
Table 1. CS5512/13 Output Conversion Data Register Description (Flags + 20 bits). ................. 18 Table 2. CS5510/11 Output Conversion Data Register Description (Flags + 16 bits). ................. 18 Table 3. CS5510/11/12/13 Output Coding. ................................................................................... 18 Table 4. Digital Filter Response at 32.768 kHz............................................................................. 19 Table 5. Device Ordering Information ........................................................................................... 23
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1. CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS
(TA = 25 C; V+ = 5 V 5%; V- = 0 V; VREF = 2.5 V (relative to V-); CS5510/12, SCLK = 32.768 kHz; CS5511/13, fosc = 64 kHz 32 kHz; OWR (Output Word Rate) = 53.5 Sps for CS5510/12; OWR = 107 Sps 50% for CS5511/13) (See Note 1.) Parameter Accuracy Linearity Error (CS5510/11) Linearity Error (CS5512/13) No Missing Codes (CS5510/11) No Missing Codes (CS5512/13) Bipolar Offset (CS5510/11) Bipolar Offset (CS5512/13) Offset Drift Over Temperature Gain Drift Over Temperature Analog Input Common Mode + Signal on AIN+ or AINDual Supply Input Range (Bipolar) Common Mode Rejection Input Capacitance CVF Current AIN+, AIN(Note 6) |(AIN+ - AIN-)/(VREF - V-)| dc 50, 60Hz (CS5510/12) V72 80 120 120 12 10 V+ 88 V % VREF dB dB pF nA (Note 2) (Note 2) (Notes 2 and 3) (Note 3) 16 20 0.0015 0.0007 3 40 60 1 0.003 0.0015 7 100 % FS % FS Bits Bits LSB16 LSB20 nV/C ppm/C Min Typ Max Unit
Typical Noise (Notes 4, 5 and 7) Output Word Rate (Hz) 53.5 -3 dB Filter Frequency (Hz) 12.5 Noise (V RMS) 7.5
Notes: 1. Specifications guaranteed by design, characterization, and/or test. 2. Specification applies to the device only and does not include any effects by external parasitic thermocouples. 3. Drift over specified temperature range after power-up at 25 C. 4. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25 C. 5. For peak-to-peak noise multiply by 6.6. 6. See the section of the data sheet which discusses Analog Input Models. 7. For CS5511/13, OWR = 107 Sps 50%.
Specifications are subject to change without notice.
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ANALOG CHARACTERISTICS (Continued)
Parameter Voltage Reference Input Range Input Capacitance CVF current Power Supplies Supply Voltages DC Power Supply Currents IV+ {(V+) - (V-)} (Note 9) CS5510 CS5511 CS5512 CS5513 CS5510 CS5511 CS5512 CS5513 (Note 10) CS5510 CS5511 CS5512 CS5513 (Note 11) 4.75 5 275 290 360 385 275 290 360 385 1.4 1.5 1.8 1.9 10 85 85 5.25 360 380 470 500 360 380 470 500 1.9 2.0 2.5 2.7 V A A A A A A A A mW mW mW mW W dB dB {(VREF) - (V-)} (Note 8) 0.250 2.5 7 6 (V+) - (V-) V pF nA Min Typ Max Unit
IV-
Power Consumption
Sleep Power Supply Rejection Notes: 8. 9. 10. 11. dc Positive Supply dc Negative Supply
VREF is referenced to V- and must be less than or equal to V+. Due to current through the CS pin, IV+ and IV- may not always be the same value. All outputs unloaded. All inputs CMOS levels (> (V+ - 0.6 V) or < (V- + 0.6 V)). CS must be inactive (logic high) during sleep to meet this power specification.
DIGITAL CHARACTERISTICS
(TA = 25 C; V+ = 5 V 5%; V- = 0 V) (See Notes 1 and 12.) Parameter High-Level Input Voltage: Low-Level Input Voltage: Input Current: High-Level Output Voltage: Low-Level Output Voltage: Input Leakage Current 3-State Leakage Current
CS and SCLK
Symbol VIH
CSLow
Min V+ - 0.45 -
Typ 0.015 -
Max VL1 VL1 1.0 (CSLow) + 0.6 10 10
Unit V V V mA V V A A
(Note 13) CS SCLK (Note 14) CS SDO, Isource = 5.0mA (Note 14) SDO, Isink = 1.0mA SCLK SCLK
VIL ICS VOH VOL Iin IOZ
(V+) - 0.6 -
Notes: 12. All measurements performed under static conditions. 13. VL1 is 0.5 (V+ - V-) + 0.6 V + V-. 14. The CS signal provides the sink current path for the SDO pin when CS is low. The external drive logic to CS, therefore, must be able to handle the logic-low current drive levels for all devices attached to SDO. The voltage specified for SDO is relative to CSLow. See Section 2.3.1, "Digital Logic Levels" and Figure 11 for more details.
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DYNAMIC CHARACTERISTICS
Parameter Modulator Sampling Frequency Output Word Rate Filter Settling Time to 1/2 LSB (Full Scale Step) CS5510/12 CS5511/13 CS5510/12 CS5511/13 Symbol fs fs OWR OWR ts Ratio SCLK/4 fosc/4 SCLK/612 fosc/612 4/OWR Units Hz Hz Sps Sps s
ABSOLUTE MAXIMUM RATINGS
(V- = 0 V) (See Note 15.) Parameter DC Power Supplies (Note 16) Positive Negative (Notes 17 and 18) (Note 19) AIN pins Symbol V+ VIIN IOUT PDN VINA VIND TA Tstg Min -0.3 -6.0 (V-)+(-0.3) (V-)+(-0.3) -40 -65 Typ Max +6.0 +0.3 10 25 400 (V+)+0.3 (V+)+0.3 +85 +150 Unit V V mA mA mW V V C C
Input Current, Any Pin Except Supplies Output Current Package Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature
Notes: 15. All voltages with respect to V-. 16. V+ and V- must satisfy 0.0V {(V+) - (V-)} +6.0 V. 17. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins. 18. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power supply pin is 50 mA. 19. Total power dissipation, including all input currents and output currents. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
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SWITCHING CHARACTERISTICS - CS5510/12
(TA = 25 C; V+ = 5 V 5%; V- = 0 V; Input Levels: Logic 0 = 0 V, Logic 1 = V+; CL = 50 pF) Parameter Master Clock Timing Master Clock Frequency (CS5510) Master Clock Frequency (CS5512) Master Clock Duty Cycle Rise Times (Note 21) CSB SCLK SDO (Note 21) CSB SCLK SDO trise tfall 10 10 200 10 2 2 200 50 32.768 32.768 1.0 10 130 200 2000 60 60 150 150 150 s s ns kHz kHz s s s s ns ns ns ns 50 1.0 10 s s ns (Note 20) SCLK (Note 20) SCLK 10 10 40 32.768 32.768 130 200 60 kHz kHz % Symbol Min Typ Max Unit
Fall Times
Serial Port Timing Serial Clock Frequency (CS5510) Serial Clock Frequency (CS5512) SCLK High to Enter Sleep SCLK Low to Exit Sleep Serial Clock SDO Read Timing
CS to Data Valid
(Note 22) SCLK (Note 22) SCLK (Note 22) Pulse Width High Pulse Width Low tSLP t1 t2 t3 t4 t5 t11 (Note 22) tWAKE
SCLK Falling to New Data Bit
CS Rising to SDO Hi-Z CS Falling to SCLK Rising
Notes: 20. Device parameters are specified with 32.768 kHz clock; however, clocks up to 130 kHz (CS5510) or 200 kHz (CS5512) can be used for increased throughput. Higher clock rates will result in degraded linearity specifications, as shown in Figures 14 and 15. 21. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF. 22. On the CS5510/12, the serial clock input (SCLK) provides the master clock to operate the converter as well as the serial data clock used to read conversion data. If SCLK is held high (logic 1) for tSLP or longer, the CS5510/12 enters sleep. To exit from sleep mode, SCLK must be held low (logic 0) for tWAKE or longer.
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SWITCHING CHARACTERISTICS - CS5511/13
(TA = 25 C; V+ = 5 V 5%; V- = 0 V; Input Levels: Logic 0 = 0 V, Logic 1 = V+; CL = 50 pF) Parameter Internal Oscillator Timing Internal Oscillator Frequency Internal Oscillator Drift Over Temperature Serial Port Timing Serial Clock Frequency SCLK High to Enter Sleep SCLK Low to Exit Sleep Rise Times (Note 24) SCLK (Notes 24 and 25) (Note 26) CSB SCLK SDO (Note 26) CSB SCLK SDO Pulse Width High Pulse Width Low tSLP trise tfall t6 t7 t8 t9 t10 t11 200 200 200 50 1.0 10 150 150 150 s s ns ns ns ns ns ns ns 50 1.0 10 s s ns (Notes 24 and 25) tWAKE 200 10 2 2000 MHz s s (Note 23) fosc 32 64 -0.02 100 kHz %/C Symbol Min Typ Max Unit
Fall Times
Serial Clock SDO Read Timing
CS to Data Valid
SCLK Falling to New Data Bit
CS Rising to SDO Hi-Z CS Falling to SCLK Rising
Notes: 23. The internal oscillator in the CS5511/13 provides the master clock for performing conversions. Data is retrieved from the serial port using the SCLK input pin. 24. The minimum SCLK rate for the CS5511/13 assumes that SCLK is logic 0 when idle. When data is being read from the ADC, SCLK must be burst at a minimum rate of 10 kHz and with a minimum of a 10 percent duty cycle. Rates slower than this can potentially put the ADC into sleep as the sleep mode is entered after SCLK is logic 1 for tSLP time. 25. On the CS5511/13, the serial clock (SCLK) is used to transfer data from the CS5511/13. If SCLK is held high (logic 1) for tSLP or longer, the CS5511/13 enters sleep mode. To exit from sleep mode, SCLK must be held low (logic 0) for tWAKE or longer. 26. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
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CS
t3 t5
SDO
M SB
t11 t4
M S B -1
t2
LSB
SCLK
t1
Figure 1. SDO Read Timing CS5510/12 (Not to Scale).
CS
t8 t10
SDO
M SB
t11 t9
M S B -1
t7
LS B
SCLK
t6
Figure 2. SDO Read Timing CS5511/13 (Not to Scale).
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2. GENERAL DESCRIPTION
The CS5510/11/12/13 are low-cost, easy-to-use, analog-to-digital converters (ADCs) which use charge balance techniques to achieve 16-bit (CS5510/11) and 20-bit (CS5512/13) performance. The ADCs are available in a space-efficient, 8-pin, SOIC package and are optimized for measuring signals in weigh scale, process control, and other industrial applications. To accommodate these applications, the ADCs include a fourth-order modulator and a digital filter. When configured with an external master clock of 32.768 kHz, the filter in the CS5510/12 provides better than 80 dB of simultaneous 50 and 60 Hz line rejection, and outputs conversion words at 53.5 Sps. The CS5511/13 include an on-chip oscillator which eliminates the need for an external clock source. The CS5510/11/12/13 ADCs are designed to operate from a single +5 V supply or a variety dual-supply configurations and are optimized to digitize bipolar signals in industrial applications. To achieve low cost, the CS5510/11/12/13 family of converters have no on-chip calibration features. The CS5510/11/12/13 offer very low offset drift, low gain drift, and excellent linearity. ferential voltage reference (VREF - V-). This translates to typically 4.0 V fully differential when the reference voltage between VREF and V- is 5 V, and typically 2.0 V fully differential at 2.5 V.
Note: When a smaller reference voltage is used, the resulting code widths are smaller. Since the output codes exhibit more changing codes for a fixed amount of noise, the converter appears noisier.
2.1.1
Analog Input Model
Figure 3 illustrates the input model for the AIN pins. The model includes a coarse/fine charge buffer which reduces the dynamic current demands from the signal source. The buffer is designed to accommodate rail-to-rail (common-mode plus signal) input voltages. Typical CVF (sampling) current is about 10 nA. Application Note 30, "Switched-capacitor A/D Input Structures", details various input architectures.
2.2
Voltage Reference Input
2.1
Analog Input
The CS5510/11/12/13 provides a differential input span of approximately (0.80 0.08) times the dif-
The voltage between the VREF and V- pins of the converter determines the voltage reference for the converter. This voltage can be as low as 250 mV, or as great as (V+) - (V-). The VREF pin can be connected directly to the V+ pin. This will establish a voltage reference equal to (V+) - (V-) for the converter. The effective resolution of the part (noisefree bits for a single sample with no averaging) will vary with VREF. Figure 4 shows how the VREF voltage affects the noise-free resolution of the
1 Fine
1 Coarse AIN Vo s 2 5 mV i n = f Vos C f = 32.768 kHz C = 12 p F
Figure 3. Input models for AIN+ and AIN- pins.
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CS5512/13. The CS5510/11 follow the same curve, but are limited to 16 bits of resolution. Note that the reference voltage should not be established prior to having the supply voltages on the V+ and V- pins. nal reference. Typical CVF (sampling) current is about 6 nA (See Figure 5). The nominal input span of the converter is defined to be a bipolar span equal to (VREF - V-)*(0.80 0.08).
2.2.1
Voltage Reference Input Model
2.3
Power Supply Arrangements
Figure 5 illustrates the input model for the VREF pin. It includes a coarse/fine charge buffer which reduces the dynamic current demand of the exter-
17
16 Effective Bits
15
The CS5510/11/12/13 are designed to operate from single or dual supplies. Figure 6 illustrates the CS5510/11/12/13 connected with a single +5 V supply to measure differential inputs relative to a common mode of 2.5 V. Figure 7 illustrates the CS5510/11/12/13 connected with 2.5 V analog supplies to measure ground-referenced, bipolar signals. It is not necessary that the dual supples on the ADCs be balanced, however, they must sum to five volts. Figure 8 illustrates the ADCs configured with V+ = +3.3 V and V- = -1.7 V, accommodating a +3.3 V digital supply.
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2.3.1
Digital Logic Levels
13 0 0.5 1 1.5 2 2.5 VREF (V) 3 3.5 4 4.5 5
Figure 4. CS5512/13 Measured Noise-Free Bits vs. VREF.
The many power supply configurations available in the CS5510/11/12/13 allow for a wide range of digital logic levels. The logic-high input and output levels are determined by the V+ pin. The logic-low output on SDO is referenced to and driven by the current logic-low voltage on CS. Since the CS5510/11/12/13 do not include a dedicated
1
Fine
2 Coarse VREF Vo s 2 5 mV i n = f Vo s C f = 32.768 kHz C = 7pF
Figure 5. Input model for VREF pin.
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+5.0 V Supply
0.1 F
6 V+
1 Voltage Reference + 2 Differential Input + ( 80% VREF)
3
V+ = 5.0 V
VREF CS5510/11/12/13 AIN+ CS SDO AINSCLK
4 8
Serial Data Interface
5 Clock Source (Required for CS5510/12 Applications)
Common Mode = 0 to V+
+ -
V7
Figure 6. CS5510/11/12/13 Configured with a +5.0 V Analog Supply.
+2.5 V Supply
0.1 F
6 V+ 1 Reference + Voltage 2 Differential Input ( 80% VREF) + 3 AINSCLK Common Mode = + V+ to VVREF CS5510/11/12/13
AIN+
V+ = 2.5 V
CS SDO
4 8 Serial Data Interface
5 Clock Source (Required for CS5510/12 Applications)
V-2.5 V Supply 7 0.1 F Implies the ground return between the two supplies.
Figure 7. CS5510/11/12/13 Configured with 2.5 V Analog Supplies.
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+3.3 V/+3.0V Supply
0.1 F 6 V+ 1 Voltage Reference + 2 VREF CS5510/11/12/13
AIN+
V+ = 3.3 V/3.0V
CS SDO
4 8 Serial Data Interface
Differential Input ( 80% VREF)
+ 3 AIN-
SCLK Common Mode = + V+ to V-
5 Clock Source (Required for CS5510/12 Applications)
V-1.7 V/-2.0V Supply 7
0.1 F
Implies the ground return between the two supplies.
Figure 8. CS5510/11/12/13 Configured with V+ = +3.3 V and V- = -1.7 V; or V+ = +3.0 V and V- = -2.0 V.
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ground pin, CSLow defines the logic-low level for the digital interface. Figures 9 and 10 illustrate the threshold levels of the CS5510/11/12/13 serial interface (CS, SCLK, and SDO). To accommodate opto-isolators, the SCLK input is designed with a Schmitt-trigger to allow an optoisolator with slower rise and fall times to directly drive the pin. Additionally, SDO is capable of sinking up to 1 mA or sourcing up to 5 mA to directly drive an opto-isolator LED. SDO will have less than a 600 mV loss in the drive voltage when sinking or sourcing its current. As shown in Figure 11, the CS signal provides the sink current path for the SDO pin when its voltage is low (i.e. the voltage specified for SDO is relative to CSLow.).
2.4.1
External Clock Source for CS5510/12
The user must provide an external (CMOS compatible) clock to the CS5510/12. The clock is input to SCLK where it is then divided down to provide the master clock for the ADC. The output word rate (OWR) for the CS5510/12 is derived from the SCLK, and is equal to SCLK/612. Figure 12 illustrates an external 32.768-kHz, CMOS-compatible clock oscillator that a user might consider. Another clock generation option is to use a microcontroller. Some microcontrollers have dedicated timer/counter circuitry which can generate a clock signal on an output pin with no software overhead. Such a microcontroller circuit is shown in Figure 13. Note that the CS5510 can operate with an external, CMOS-compatible clock at frequencies up to 130 kHz, and the CS5512 can operate with an external clock of up to 200 kHz with a maximum 22 ns of jitter. Linearity performance is degraded slightly with higher clock speeds, as shown in Figures 14 and 15. The noise performance of the parts, however, is not affected by higher clock speeds.
2.4
Clock Generator
The CS5510/12 and CS5511/13 provide distinct modes for generating the master clock for the ADCs. The CS5510/12 uses the SCLK input pin as its operating clock. The CS5511/13 has an on-chip oscillator that provides its master clock. The SCLK pin on the CS5511/13 is used only to read data and to put the part into sleep mode.
2.4.2
V+
Internal Oscillator for CS5511/13
= VIH = V+ - 0.45V VIL = 0.5 ( V+ - V-) + 0.6V + VCS LOW
V-
The CS5511/13 includes an on-chip oscillator. This oscillator provides the master clock for the CS5511/13 and oscillates at 64 kHz 32 kHz. The
V+ Output Drive Logic
Figure 9. CS and SCLK Digital Input Levels.
5 mA Max Source
V+
SDO (from SDO Control Logic)
VOH= V+ - 0.6V
1 mA Max Sink
VOL = CS LOW + 0.6V VIL
CS LOW V-
CS (to CS Control Logic)
Figure 10. SDO Digital Output Levels.
Figure 11. Serial Port Output Drive Logic.
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VD+ = 2.5 V to 5.25 V Fairchild NC7SU04 or 1/6 74HCU04 To SCLK
Counter/Timer
SCLK
10 M
49.9 K
CS5510/12 CS SDO C
47 pF
32.768 kHz
22 pF
Figure 12. External (CMOS Compatible) Clock
Figure 13. Using a Microcontroller as a Clock
output word rate (OWR) for the CS5511/13 is derived from the internal oscillator, and is equal to fosc/612. Due to the part-to-part variances in the oscillator frequency, the OWR of the CS5511/13 can vary between 53 Sps and 159 Sps.
2.5
Performing Conversions
After power and a clock source are established to the CS5510/11/12/13, the ADCs begin performing conversions. The three sections that follow explain how to read conversion data from each ADC, and
decode the conversion word into the respective flag and data bits. Keep in mind that in the CS5510/12, SCLK provides the external clock source for the converter. Data is clocked from the CS5510/12 at the rate set by the external clock source (typically 32.768 kHz). The CS5511/13 provides an on-chip oscillator for the master clock. In the CS5511/13, SCLK is asynchronous to the onchip oscillator and can be clocked at a rate up to 2 MHz.
0.004 Linearity Error (%FS)
0.003 Linearity Error (%FS) 0.0025 0.002 0.0015 0.001 0.0005 0 0 20 40 60 80 100 120 140 160 180 200 SCLK (kHz) OWR = SCLK 612
OWR = SCLK 612
0.0035 0.003 0.0025 0.002 0.0015 0.001 0.0005 0 10 30 50 70 SCLK (kHz) 90 110 130
Figure 14. Typical Linearity Error for CS5510.
Figure 15. Typical Linearity Error for CS5512.
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2.5.1 Reading Conversions CS5510/12
by a new conversion word when the new conversion data is available.
After power-up, the CS5510/12 will begin converting once a clock source is applied to the SCLK pin. When a conversion has completed, and there is new data in the output register, the SDO line will fall to a logic-low level if CS is also at a logic-low state (SDO will always be high-impedance when CS is high). If CS is low at the end of the conversion cycle, SDO will fall on the rising edge of an SCLK. After SCLK falls, the next SCLK cycle (high, then low) will begin clocking out the data. The first data bit therefore, is 1-1/2 SCLK cycles wide. Twenty-four SCLK cycles (after the initial high-low transition) are needed to retrieve the conversion word from the device (see Figures 16 and 17). The data bits can be read on the rising edge of SCLK, and the next data bit is output to SDO on the falling edge of SCLK. Once the entire data word has been read, SDO will return to a logic-high state until there is a new conversion word available. If CS is at a logic-high at the end of the conversion cycle, the data will not be shifted out of the part until CS is brought to a logic-low state during the next conversion cycle. If a new conversion becomes available while the current data is being read, the data register will not be updated, and the new conversion word will be lost. The user need not read every conversion. If the user chooses not to read a conversion, CS should remain at a logic-high state for the duration of the conversion cycle. Note that if CS goes to a logic-high state during a read, the current conversion data will be lost and replaced
2.5.2
Reading Conversions CS5511/13
After power-up, the CS5511/13 begins converting and updating the output register. When there is new data in the output register (at the end of a conversion cycle) the SDO line will fall to a logic-low level if CS is also at a logic-low state (SDO will always be high-impedance when CS is high). Twenty-four SCLK cycles are needed to retrieve the conversion word from the device (see Figures 18 and 19). The data bits can be read on the rising edge of SCLK, and the next data bit is output to SDO on the falling edge of SCLK. Once the entire data word has been read, SDO will return to a logic-high state until there is a new conversion word available. If new conversions become available while the current data is being read, the data register will not be updated, and the new conversions will be lost. The user need not read every conversion. If the user chooses not to read a conversion after SDO falls, SDO will rise seventeen oscillator clock cycles (of the internal oscillator) before the next conversion word is available and then fall again to signal that the conversion is complete. Note that if a conversion word is not read before the next conversion word is ready, or if CS goes to a logic-high state during a read, the current conversion data will be lost and replaced by a new conversion word when the new conversion data is available.
CS
SC LK
SDO
0
OF
OD
0
0
0
0
0
M SB
LSB
0
0
D a ta T im e 24 SC LKs
Figure 16. Data Word Timing for the CS5510. 16 DS337F3
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2.5.3 Output Coding
20 bits are the conversion data, which is output MSB first (Table 1). Bits D22-D21 are the two flag bits. The OF (Overrange Flag) bit is set to a logic 1 any time the input signal is more positive than positive full scale, or more negative than negative full scale. It is cleared back to logic 0 whenever a conversion word occurs which is not overranged. The OD (Oscillation Detect) bit is set to a logic 1 any time that an oscillatory condition is detected in the modulator. This does not occur under normal operating conditions, but may occur whenever the input to the converter is ex-
As shown in Tables 1 and 2, the CS5510/11/12/13 present output conversions as 24-bit conversion words. The first bit of the conversion word indicates that a conversion is done through SDO falling from a logic high to a logic low level. The first and the fourth bits output will always be zero. The second and third bits are error flags, representing an overflow or oscillation condition. In the CS5510/11, there are four more bits of zero, and the remaining 16 bits are the conversion data, output MSB first (Table 2). In the CS5512/13, the final
CS
SCLK
SDO
0
OF
OD
0
0
0
0
0
M SB
LSB
0
0
D ata T im e 24 S C L K s
Figure 17. Data Word Timing for the CS5511.
CS
SC LK
SDO
0
OF OD
0
M SB
LSB
0
0
D a ta T im e 24 SC LKs
Figure 18. Data Word Timing for the CS5512.
CS
S C LK
SDO
0
OF
OD
0
M SB
LS B
0
0
D a ta T im e 24 S C LK s
Figure 19. Data Word Timing for the CS5513.
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Bipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 LSB Two's Complement (20-Bit) 7FFFF 7FFFF ----7FFFE 00000 ----FFFFF 80001 ----80000 Two's Complement (16-Bit) 7FFF 7FFF ----7FFE 0000 ----FFFF 8001 ----8000
-0.5 LSB
-VFS+0.5 LSB
Note: VFS in the table equals the voltage between AIN+ and AIN-. See text about error flags under overrange conditions. Table 3. CS5510/11/12/13 Output Coding.
cessively overranged. If the OD bit is set, the conversion data bits can be completely erroneous. The OD flag bit will be cleared to logic 0 four output words after the modulator becomes stable again. The OD flag can occur independent of OF with a spike on the input. Both flag bits should be tested if any overrange condition occurs. Table 3 illustrates the output coding for the CS5510/11/12/13. Conversions are output as two's complement values representing bipolar input signals.
2.5.4
Digital Filter
The CS5510/11/12/13 have a modified Sinc4 digital filter that provides CLK/612 Hz conversion rates
(CLK represents SCLK for the CS5510/12 and the internal oscillator for the CS5511/13). The filters are optimized to yield better than 80 dB rejection between 47 Hz to 63 Hz (i.e. 80 dB minimum rejection for both 50 Hz and 60 Hz) when the master clock is 32.768 kHz. The filter has a response as shown in Figure 20. Table 4 shows the filter response for frequencies from 38 Hz to 71 Hz. Note that the response of the CS5511/13 will be similar, but the frequencies scale with the on-chip oscillator's frequency, which can be from 32 kHz to 96 kHz (i.e. conversion rates can vary between 53 Sps to 159 Sps). Further note that after initial power up, or after returning from sleep mode, the filter requires four conversion cycles to produce a
D23 0 D11 11
D22 OF D10 10
D21 OD D9 9
D20 0 D8 8
D19 MSB D7 7
D18 18 D6 6
D17 17 D5 5
D16 16 D4 4
D15 15 D3 3
D14 14 D2 2
D13 13 D1 1
D12 12 D0 LSB
Table 1. CS5512/13 Output Conversion Data Register Description (Flags + 20 bits).
D23 0 D11 11
D22 OF D10 10
D21 OD D9 9
D20 0 D8 8
D19 0 D7 7
D18 0 D6 6
D17 0 D5 5
D16 0 D4 4
D15 MSB D3 3
D14 14 D2 2
D13 13 D1 1
D12 12 D0 LSB
Table 2. CS5510/11 Output Conversion Data Register Description (Flags + 16 bits). 18 DS337F3
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0 -20 -40
CS5510/12 SCLK = 32.768 kHz
Magnitude (dB)
-60 -80 -100
47 Hz
-120 -140 0 20 40 60
63 Hz
80
100
120
Frequency (Hz)
Figure 20. Digital Filter Response.
Frequency (Hz) 38 39 40 41 42 43 44 45 46
Rejection (dB) 37 39 42 46 49 54 58 64 72
Frequency (Hz) 47 48 49 50 51 52 53 54 55
Rejection (dB) 84 92 88 92 105 89 86 85 87
Frequency (Hz) 56 57 58 59 60 61 62 63 64
Rejection (dB) 91 109 94 89 88 92 104 84 77
Frequency (Hz) 65 66 67 68 69 70 71 -
Rejection (dB) 73 69 66 64 63 61 60 -
Table 4. Digital Filter Response at 32.768 kHz.
valid conversion due to the modified Sinc4 filter characteristics.
2.5.5
Multiplexed Applications
The settling performance of the CS5510/11/12/13 in multiplexed applications is determined by the Sinc4 filter. To settle, a step input requires 4 full conversion cycles after the analog input has switched. In this case, the throughput is reduced by a factor of four as the first three conversions after the step is applied will not be fully settled. If the application does not require the maximum throughput possible from the ADC, the multiplexer can be switched at any time. In this case, the system must wait for at least five conversion cycles for a fully-settled result from the ADC.
If maximum throughput is required in a multiplexed application, the multiplexer must be switched at the correct time during the data collection process. For maximum throughput with the CS5510/12, switching of a multiplexer should occur 595 SCLK cycles after SDO falls. For maximum throughput with the CS5511/13, switching of a multiplexer should occur on the rising edge of SDO during a conversion in which the data word is not read. The conversion data that is immediately available when SDO falls again is valid, and represents the analog input from the previous multiplexer setting. The next three conversions from the part will be unsettled values, and the fourth conversion will represent a fully-settled result from the new multiplexer setting. The multiplexer should be switched again at the appro-
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priate time during the third conversion cycle to ensure the maximum possible throughput. will be equivalent to: 0x7FFF*Vcal/(0.80*Vref) for the CS5510/11, and 0x7FFFF*Vcal/(0.80*Vref) for the CS5512/13. The gain error (GE) is equal to: (Cr - ZP)/Ci. To correct for both offset and gain error in subsequent conversions, subtract the offset error, and then divide by the gain error.
2.6
Digital Off-chip System Calibration
The CS5510/11/12/13 exhibit excellent linearity with low offset and gain drift, without the need for calibration. If precision voltage measurements are required by the system, however, software-based offset and gain calibration can be performed by the system. To perform a software offset calibration, the "zeropoint" of the system should be established by applying an input to the system equal to zero. Then, the user can obtain a conversion and store it in memory as the system's zero point (ZP). This number can then be used as the zero point for any subsequent conversion words. In the 20-bit devices (CS5512 and CS5513), multiple conversions can be averaged to arrive at a more accurate offset value. In the 16-bit devices (CS5510 and CS5511), averaging may not be meaningful, because the noise will be below the size of one LSB when using nominal voltages for VREF (2.5 V). A software gain calibration can be performed by bringing the system to a known calibration Voltage value (Vcal) and acquiring a conversion (note that Vcal should be low enough to compensate for the possible gain error of the ADC). Multiple conversions can be averaged at this point to improve the accuracy of the calibration. The code obtained from this conversion is the real value (Cr) of the calibration Voltage input, and will differ from the ideal value. The ideal value for this conversion (Ci)
2.7
Power Consumption, Sleep and Reset
The CS5510/11/12/13 accommodates two power modes: normal and sleep. The normal mode is the default mode and is entered after power is established to the ADC. In normal mode, the ADCs typically consumes 2.5 mW. Sleep is entered when the user leaves SCLK high for at least 200 s. The ADCs are guaranteed to be in sleep after SCLK is high (logic 1) for 2 ms. The sleep mode reduces the consumed power to less than 10 W when CS is high (logic 1). If CS is low (logic 0) at this time, the SDO drive logic will still be active, and the consumed sleep power will be greater. To exit sleep and return to normal mode, the user must return SCLK low for at least 10 s. After a sleep is exited, the ADCs reset all their internal logic, including their digital filters, and begin performing conversions. Since the filters are reset, the first three conversion after returning to normal mode will not be fully settled.
2.8
PCB Layout
The CS5510/11/12/13 should be placed entirely over the analog ground. Place the analog-digital plane split immediately adjacent to the digital pins of the chip.
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3. PIN DESCRIPTIONS
VREF
1 2 3 4
8 7 6 5
SDO
AIN+
AINCS
VV+ SCLK
Control Pins and Serial Data I/O
CS - Chip Select, Pin 4
CS is a dual function pin, which determines the state of SDO, as well as the digital logic-low output level. When CS is low, SDO will be active. When high, the SDO pin will output a high-impedance state. The logic-low level of SDO will match the active-low voltage on CS.
SDO - Serial Data Output, Pin 8
SDO is the serial data output. It will output a high-impedance state if CS = 1. The logic-low level of SDO will match the active-low voltage on CS.
SCLK - Serial Clock Input, Pin 5
SCLK is the serial bit-clock which controls the shifting of data from the ADCs. This input goes through a Schmitt trigger to allow for slow rise and fall time signals. If held high, the device will enter sleep mode. In the CS5510/12, this input is also used as a master clock source which determines conversion speeds and throughput. In the CS5511/13, SCLK is only used to read the conversion data and put the part in sleep mode.
Measurement and Reference Inputs
AIN+, AIN- - Differential Analog Input, Pins 2, 3
Differential input pins into the device
VREF - Voltage Reference Input, Pin 1
Input Voltage which establishes the voltage reference, with respect to V-, for the on-chip modulator
Power Supply Connections
V+ - Positive Power, Pin 6
Positive supply voltage
V- - Negative Supply, Pin 7
Negative supply voltage
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4. SPECIFICATION DEFINITIONS
Linearity Error
The deviation of a code from a straight line which connects the two end points of the A/D Converter transfer function. One end point is located 1/2 LSB below the first code transition and the other end point is located 1/2 LSB beyond the code transition to all ones. Units in percent of full-scale.
Differential Nonlinearity
The deviation of a code's width from the ideal width. Units in LSBs.
Full Scale Error
The deviation of the last code transition from the ideal [{(VREF) - (V-)} - 3/2 LSB]. Units are in LSBs.
Bipolar Offset
The deviation of the mid-scale transition (111...111 to 000...000) from the ideal (1/2 LSB below the voltage on the AIN- pin). Units are in LSBs.LK
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5. ORDERING INFORMATION
Device Number CS5510-AS CS5510-ASZ (Lead Free) CS5511-AS CS5511-ASZ (Lead Free) CS5512-BS CS5512-BSZ (Lead Free) CS5513-BS CS5513-BSZ (Lead Free) Oscillator External 16 Bits Internal -40C to +85C External 20 Bits Internal 0.0015% 8-pin SOIC 0.003% Resolution Linearity Error (Max) Temperature Range Package
6.
ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION
Model Number Peak Reflow Temp 240 C 260 C 240 C 260 C 240 C 260 C 240 C 260 C MSL Rating* 2 3 2 3 2 3 2 3 Max Floor Life 365 Days 7 Days 365 Days 7 Days 365 Days 7 Days 365 Days 7 Days
CS5510-AS CS5510-ASZ (Lead Free) CS5511-AS CS5511-ASZ (Lead Free) CS5512-BS CS5512-BSZ (Lead Free) CS5513-BS CS5513-BSZ (Lead Free)
* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.
7.
REVISION HISTORY
Date MAR 2005 AUG 2005 Changes Added lead-free device ordering information. Updated lead-free device ordering information. Added MSL data. F2 F3
Revision
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8. PACKAGE DIMENSIONS
8L SOIC (208 MIL BODY) PACKAGE DRAWING
E
H
1 b c
D SEATING PLANE e A1
A L
DIM A A1 b C D E e H L
MIN 0.076 0.004 0.013 0.006 0.206 0.204 0.040 0.302 0.019 0
INCHES NOM 0.080 0.007 0.016 0.008 0.208 0.208 0.050 0.310 0.025 4
MAX 0.084 0.010 0.020 0.010 0.210 0.212 0.060 0.318 0.030 8 EIAJ PACKAGE
MIN 1.93 0.10 0.33 0.15 5.23 5.18 1.02 7.67 0.48 0
MILLIMETERS NOM 2.03 0.175 0.406 0.20 5.28 5.28 1.27 7.88 0.64 4
MAX 2.13 0.25 0.51 0.25 5.33 5.38 1.52 8.08 0.76 8
Controlling Dimension is Inches
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